lecture9.computerArchiture

L1 split cache
multiple ports mean multiple access
cause larger overhead

eg: avoid hazard, multiple ports

mltiple exclusion and mutiple inclusion:
L1 and L2
L1 or L2

multiple level cache

1. write through and write back
   readhit: read hit time + miss penalty
   read miss: read hit time + miss penalty
   write hit: write hit time + wirte time to lower level
   wirte miss: write hit time + write time to lower level + read block from lower level

2. write through plus non-write allocate

3. write back and write allocate
   read hit: read hit time
   read miss: read hit time + miss penalty plus time to write dirty block if it is dirty

write hit: